The present invention generally relates to the field of semiconductor memories, particularly to non-volatile memories and, even more particularly, to memories based on phase-change materials, also known in the art as ovonic unified memories.
Ovonic unified or phase-change memories are an emerging type of electrically-alterable non-volatile semiconductor memories. These memories exploit the properties of materials (phase-change materials) that can be reversibly switched between an amorphous phase and a crystalline phase when heated. A phase-change material exhibits different electrical characteristics, particularly a different resistivity, peculiar of each one of the two phases; thus, each material phase can be conventionally associated with a corresponding one of the two logic values, “1” and “0”.
Typically, the memory includes a matrix of phase-change memory cells, arranged in rows and columns with associated word lines and bit lines, respectively. Each memory cell consists of a storage element connected in series to an access element; the series of the storage element and the access element is connected between the respective word line and the respective bit line.
The memory cells can be selected for a reading operation, for example, by applying suitable voltages to the respective word lines and suitable current or voltage pulse to the respective bit lines. During a reading operation, a read current pulse causes the charging of stray capacitances intrinsically associated with the bit lines, and, accordingly, a corresponding transient (the duration of which depends on the state of the storage element) of a bit line voltage at each selected bit line. The respective bit line voltage raises towards a corresponding steady-state value Vfinal, depending on the resistance of the storage element, i.e., on the logic value stored in the selected memory cell.
The logic value stored in the memory cell is evaluated by sense amplifiers of the memory. A sense amplifier may include a comparator input receiving the bit line voltage and another comparator input from a suitable reference voltage. The reference voltage which may be band-gap based for temperature and voltage compensation is generated, for example, by a voltage which may be either adjusted at probe or packaging or even in the field based on array bit testing or may be generated using a service reference memory cell. If using a reference cell charged by current during read, similarly to the bit line voltage, the reference voltage may undergo a transient during a reading operation.
In the case in which the bit line voltage is higher than the reference voltage, this situation, for example, is decreed to correspond to a stored logic value “0”, whereas in the case in which the bit line voltage is smaller than the reference voltage, this situation is decreed to correspond to the stored logic value “1”.
If the current flowing through the selected memory cell exceeds a threshold current value, typically of only few microamperes, a heating by a Joule effect of the storage element is caused, which, consequently, may be spuriously programmed. In order to avoid spurious programming of the storage elements, for example, the read current may be limited to a value lower than the oum threshold current.
Such a small current may involve a relatively slow charging of the bit line stray capacitances, which implies an increase of the time required for a reading operation. In particular, in the case the memory is adapted to perform reading operations in a burst way, an initial latency, i.e., a time range between a first time in which a first address is provided to the memory and a second time in which the first data read is output, is increased. The request for faster and faster reading operation consequently prefers smaller and smaller initial read access cycle times and access latency delay.